In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Phase detectors are used in synchronous circuits such as phase-locked loops (PLLs) and delay-locked loops (DLLs) to provide control signals for adjusting a variable delay value to establish a predetermined phase relationship between the internal and external clock signals. For example, where the desired phase relationship between the two clock signals is zero degrees, the phase detector will detect any phase difference between the two clock signals and generate a control signal that is received by a shift register to advance or delay a local signal. Some phase detectors for DLL circuits utilize an arbiter-based detection, where an arbiter circuit receives the two clock signals and makes a decision to add a delay or remove a delay depending on which signal was received first. FIG. 1 shows a block diagram of a conventional phase detector 100 that includes arbiters 115, 117, 119. The phase detector 100 receives two clock signals DLLREF and DLLFB, and a phase detector enable signal ENPD. The DLLREF signal is typically a reference or external clock signal, and the DLLFB signal is an internal clock signal, such as from the feedback loop of a DLL. The phase detector 100 includes two arbiters 115, 117 for comparing the received DLLREF and DLLFB signals.
While a single arbiter, such as the upper arbiter 115 can be used to determine the phase difference of the two received signals, the second arbiter 117 is included in the design to create a two-arbiter scheme that is used to add some hysteresis to the phase detector 100. Some DLL designs use two-arbiter phase detector designs to provide a certain amount of hysteresis to eliminate undesired DLL loop oscillation. The DLLREF and DLLFB clock signals are received by a respective NAND gate 110a-d, along with the ENPD signal. When the NAND gates 110a-d are enabled by a high ENPD signal, each of the NAND gates 110a-d couple either the DLLREF clock signal or the DLLFB clock signal to the input of a respective fine delay line 112a-e that adds a delay to the DLLREF clock signal or the DLLFB clock signal to generate respective CLKREF1 or CLKFB1 clock signals. In the example shown in FIG. 1, the delay DL1 of fine delays 112a, 112d are greater than the delay DL2 of the fine delays 112b, 112c. As explained below, the differences in these delay DL1, DL2 establish a hysteresis for the phase detector 100. Assume initially that the DLLREF clock signal leads the DLLFB signal. The delays DL1 and DL2 are set so that the CLKFB1 signal will lead the CLKREF1 signal if the DLLREF clock signal leads the DLLFB signal by a relatively small amount that is within a hysteresis window. In other words, CLKREF1 delayed by DL1 will lag CLKFB1 delayed by the delay DL2. In such case, the upper arbiter 115 will output a high FBFIRST signal and a low REFFIRST signal. However, if the DLLREF clock signal leads the DLLFB signal by amount that is larger than the hysteresis window, the CLKREF1 clock signal will lead the CLKFB1 clock signal despite the greater delay DL1 applied on the DLLREF clock signal relative to the delay DL2 applied on the DLLFB clock signal. In such case, the upper arbiter 115 will output a high REFFIRST signal and a low FBFIRST signal. In summary, the upper arbiter 115 will output a high REFFIRST signal and a low FBFIRST signal only if the DLLREF signal leads the DLLFB signal by an amount that is greater than the hysteresis window. In all other cases, the upper arbiter 115 will output a low REFFIRST signal and a high FBFIRST signal. Therefore, a NAND gate 120a will receive a logic “1” signal from the upper arbiter 115 only if the CLKREF1 signal leads the CLKFB1 signal by an amount that is greater than the hysteresis window.
The lower arbiter 117 operates in a similar manner except that the DLLFB clock signal is delayed by the fine delay 112d to a greater extent than the DLLREF clock signal is delayed by the fine delay line 112c. Therefore, if the DLLREF clock signal leads the DLLFB clock signal the CLKREF2 signal will always lead the CLKFB2 clock signal regardless of how much the DLLREF clock signal leads the DLLFB clock signal. Therefore, if the DLLREF clock signal leads the DLLFB clock signal, the lower arbiter 117 will always output a high REFFIRST and a low FBFIRST signal. In such case, a NAND gate 120b will receive a logic “0” from the lower arbiter 117.
The lower arbiter 117 functions in response to the DLLFB clock signal leading the DLLREF clock signal in the same manner as the upper arbiter 115 functions in response to the DLLREF clock signal leading the DLLFB clock signal. Therefore, the lower arbiter 117 will output a high FBFIRST signal only if the DLLREF clock signal lags the DLLFB clock signal by more than the hysteresis window, and the upper arbiter will output a high FBFIRST signal as long as the DLLREF clock signal lags the DLLREF signal regardless of the amount the DLLREF clock signal lags the DLLFB signal. Therefore, the NAND gate 120b will receive a logic “1” signal from the lower arbiter 117 only if the CLKREF2 signal lags the CLKFB2 signal by an amount that is greater than the hysteresis window. Insofar as the upper arbiter 115 always outputs a high FBFIRST signal if the DLLREF clock signal lags the DLLFB clock signal, the NAND gate 120b outputs low if the CLKREF2 signal lags the CLKFB2 signal by an amount that is greater than the hysteresis window.
In summary, the NAND gate 120a outputs a low if the DLLREF clock signal leads the DLLFB clock signal by an amount that is greater than the hysteresis window, and the NAND gate 120b outputs a low if the DLLREF clock signal lags the DLLFB signal by an amount that is greater than the hysteresis window. The NAND gates 120a,b will each output a logic “1” if the difference in phase between the DLLREF and DLLFB signals is less than the hysteresis window.
The outputs of the NAND gates 120a,b are applied to a latch 125, which samples the outputs after each phase comparison has been made. Since the decision of the arbiters 115, 117 lasts only as long as the narrowest pulse width of the input clock signals, the decision must be strobed with a matched clock. To perform this function, one of the input clock signals, the DLLREF clock signal, is applied to a model arbiter 119 through a matched fine delay 112e which has a delay DL1 that is the same delay as the delay provided by the fine delay 112a. As a result, a transition of a CLKREF3 clock signal occurs at the time a transition of the CLKREF1 clock signal occurs. The other input clock signal, the DLLFB clock signal, is provided to a NAND gate 110f, along with the ENPD signal, only for the purpose of load matching the other NAND gates 110a-d of the arbiters 115, 117. Since only the DLLREF clock signal is propagated through the model arbiter 119, the output of the NAND gate 110f is floating (not connected).
The model arbiter 119 then generates a high LATCH signal on the rising edge of the CLKREF3. This high LATCH signal causes an enabled NAND gate 120c to output an active low clock signal that is further delayed by a delay line 113 that provides at most a delay DL3 that is half the maximum period of the CLKREF1 clock signal. The total delay applied to the DLLREF signal is the delay DL1 plus a delay that is at most half the period of the CLKREF1 clock signal, which ensures the latch occurs well after whichever clock signal is last to transition high. The delay line 113 outputs a delayed active low clock signal PDCLK*, which causes the outputs of the NAND gates 120a,b to be stored in a latch 125. The latch 125 generates a high SHIFT-L signal responsive to a low at the output of the NAND gate 120a, and it generates a high SHIFT-R signal responsive to a low at the output of the NAND gate 120b. If the outputs of both NAND gates 120a,b are high, which is indicative of a phase different that is less than the hysteresis window, neither the SHIFT-L nor the SHIFT-R signal is high. The SHIFT_L and SHIFT_R signals are typically control signals for adding or removing delays to adjust the phase of the DLLFB clock signal to reduce the difference between the phase of the DLLREF clock signal and the phase of the DLLFB clock signal.
Although the two-arbiter phase detector 100 is generally reliable for DLL designs that use conventional clock speeds, there is a greater need for extremely accurate, faster phase detectors as higher clock frequencies are used. Each arbiter and each delay line of the phase detector 100 individually requires power and space to operate. Therefore, the phase detector 100 consumes excessive amounts of total power and chip space due to the multiple arbiters and delay lines included in the design.
Another limitation of the phase detector 100 is that, in many cases, particularly when the DLLREF and DLLFB clock signals are close in phase the phase detector 100 outputs a SHIFT_L or SHIFT_R output well after the time that the arbiters 115, 117 have been able to output phase decision signals. This delay in providing phase decision output signals results from the relatively long delay DL3 that the delay line 113 must provide to ensure that the outputs of the arbiters 115, 117 are not latched until both the DLLREF and DLLFB delayed by the delay lines 112 have transitioned high. This delay must be sufficient for “worst case” conditions that are as long as one-half period of the lowest frequency clock signal that will be applied to the phase detector 100. However, in many cases, the rising edge of the DLLFB clock signal will lag the DLLREF clock signal by far less than one-half period, or the clock signal will have a frequency that is far higher than the lowest frequency clock signal with which the phase detector 100 is designed to operate. In such case, the arbiters 115, 117 output phase decision signals as soon as the CLKREF and CLKFB signals delayed by the delay lines 112 have transitioned high. However, the resulting phase decision signals are not latched to provide the SHIFT_L and SHIFT_R signals from the latch 125 until well afterward. This delay in providing the SHIFT_L and SHIFT_R signals slows the operation of the phase detector 100. For example, if the phase detector 100 is used in a delay-lock loop (not shown), the slower operation of the phase detector 100 results in a delay in taking action to correct phase errors in the loop.
Other phase detectors have been designed using D-flip-flops instead of arbiters to reduce power consumption and use of chip space. However, because D-flip-flop have different setup and hold paths than of the arbiter-based systems, the phase detector has a tendency to exhibit phase bias, which may be regarded as a form of hysteresis. At high clock frequencies, the presence of phase bias or hysteresis in the phase detection increases the overall likelihood of phase detector error.
Therefore, there is a need for a highly accurate phase detector circuit operable to provide phase decisions without the effects of hysteresis or phase bias, and that does not rely on excessive delay lines or arbiters, thereby enabling a reduction in the overall size of the circuit and the consumption of power and chip space.